The present invention relates to data transmission techniques, and more particularly, to data path timing in circuitry, such as integrated circuit memory devices.
Integrated circuit devices, such as high-speed memory devices, typically include data paths that include circuits, such as sense amplifiers, that strobe input data subject to an intermittently asserted signal (e.g., an enable or clock signal). Generally, valid data input must be present at the input of such a circuit within certain timing constraints relative to the strobe signal.
An exemplary data path as might be found in an integrated circuit is illustrated in FIG. 1, and exemplary operations of the data path of FIG. 1 are illustrated in FIG. 2. At a certain point during a data access cycle, a data driver enable signal DEN is activated to cause a data driver 10 to output data. This output data passes on to an output flip-flop (FF) 40 through circuitry 20, e.g., wiring, buffers, etc., that introduces delay between when the data is produced at the output of the data driver 10 and when it appears at the input of the FF 40. If the data is not in a form that the FF 40 can handle (e.g., has insufficient swing differential), a receiver 30 (e.g., a sense amplifier) may be used to convert the data format to meet the input requirements of the FF 40. The timing of a receiver enable signal REN applied to the data receiver 30 typically needs to be such that correct data is present at the input of the data receiver 30 a certain time before the receiver enable signal REN is asserted. The receiver 30 typically needs a certain amount of time to convert the data format, after which the output FF 40 can be clocked responsive to an output clock signal OCLK.
In the conventional circuit of FIG. 1, time ten between assertion of the driver enable signal DEN and the assertion of the receiver enable signal REN is typically fixed based on a starting point in a data access cycle. The minimum cycle time of the data path is generally constrained by the timing requirements of the FF 40, as time interval t′ between the receiver enable signal REN and the output clock signal OCLK generally varies as the cycle time of the data path varies.
In designing such a data path in an integrated circuit device, such as a high-speed memory device, delay attributable to data propagation and manipulation between the data driver 10 and the data receiver 30 is typically estimated using simulations. These simulations are often used to determine a minimum time ten between assertion of the driver enable signal DEN and assertion of the receiver enable signal REN that guarantees, for a given operating envelope, that valid data will be present at the input of the data receiver 30 before the receiver enable signal REN is asserted. In particular, circuit and device models are typically used to estimate data delay in the presence of process, temperature and power supply voltage variations. Such an approach can lead to an overly conservative design for a particular device.